1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor devices and, more particularly, to the handling of integrated circuit devices throughout the manufacturing process. Specifically, the present invention is directed to a tray-based method and apparatus for handling integrated circuit devices orientated in an array of integrated circuit device stacks, each stack consisting of multiple integrated circuit devices.
2. State of the Art
During the manufacture and testing of integrated circuit (IC) devices, processing trays—also referred to as carrier trays, component trays, IC device trays, or in-process trays—are routinely used for handling large numbers of IC devices. Tray-based IC device handling systems are commonly adapted to supply IC devices to primary processing systems such as, for example, sorting and binning equipment, burn-in and electrical test systems, or any other IC device processing system as known in the art. Tray-based IC device handling systems may be configured for use with a number of different types of IC devices, including dual in-line packages (DIPs), zigzag in-line packages (ZIPs), thin small outline packages (TSOPs), small outline J-lead packages (SOJs), ball-grid arrays (BGAs), pin-grid arrays (PGAs), quad flat packages (QFPs), pad array carriers (PACs), and plastic leaded chip carriers (PLCCs).
Presently, numerous conventional processing tray designs are used with tray-based IC device handling systems. Conventional processing trays generally comprise a frame enclosing a planar, open lattice structure. The latticework forms a two-dimensional array of cells, typically comprising a plurality of rows and a plurality of columns of cells, wherein each cell is configured to receive an individual IC device. Thus, a conventional processing tray for handling IC devices provides a planar, two-dimensional array of cells wherein each cell is capable of accepting an individual IC device.
The structure and function of the tray frame and cells vary among the conventional designs. For example, in U.S. Pat. No. 5,203,452 to Small et al., individual cells can be severed from the frame to facilitate handling of an individual IC device. Similarly, in U.S. Pat. No. 5,246,129 to Small et al., rows of cells containing IC devices may be severed from the frame. Crisp et al., U.S. Pat. No. 5,636,745, disclose a system of interlocking, stackable IC device processing trays. Boardman et al., U.S. Pat. No. 5,492,223, also disclose interlocking and stackable IC device trays, but each tray is configured to hold only a single IC device. In U.S. Pat. No. 4,600,936, Khoury et al. teach the use of a reference surface within each cell of a two-dimensional array of cells to assist in the placement and alignment of an individual IC device within each cell. Murphy, U.S. Pat. No. 5,103,976, discloses a system of stackable IC device trays and spacer trays wherein oversized IC devices can be accommodated using a spacer tray disposed between two stacked IC device trays, each IC device tray consisting of a two-dimensional array of cells. In U.S. Pat. No. 5,927,503, Nevill et al. disclose a processing tray for handling IC devices comprised of a two-dimensional array of cells; however, each cell is configured to accept an insert and it is the insert that is adapted to receive at least one IC device. None of these conventional IC device processing trays have a cell capable of accepting multiple IC devices in a stacked relationship.
Another conventional processing tray design widely used within the semiconductor industry is the JEDEC tray. These trays are designed and built in compliance with standards propagated by the Joint Electronic Device Engineering Council (JEDEC). Generally, a JEDEC tray consists of a grid-like, open lattice structure that forms a planar, two-dimensional array of IC device cells. JEDEC trays are usually injection molded from plastic and vary in overall dimensions and grid-size, depending on the type of IC device the tray is designed to hold. JEDEC trays are stackable and also have surface features, such as locating and hold-down tabs, that allow the trays to be manipulated by automatic processing and testing equipment. Although a JEDEC tray itself can be disposed on top of another JEDEC tray to form a stack of multiple trays, an individual cell within the array of cells on each tray is capable of holding only a single IC device.
Within an IC device manufacturing facility, tray-based IC device handling systems are used to move processing trays, and a plurality of IC devices disposed therein, from one processing station to a subsequent processing station and, otherwise, throughout the manufacturing facility. For example, a tray-based IC device handling system may be used to move a plurality of IC devices disposed in one or more processing trays to a first processing station. The first processing station may comprise fabrication equipment, burn-in and electrical testing equipment, sorting and binning equipment, or any other appropriate IC device processing systems as are known in the art. The plurality of IC devices is transferred to the first processing station for testing, fabrication, or other manufacturing processes. After processing at the first processing station is complete, the tray-based IC device handling system transfers the plurality of IC devices to one or more processing trays and those processing trays are moved to a second processing station. The tray-based IC device handling system then transfers the plurality of IC devices to the second processing station for testing, fabrication, or other manufacturing processes.
Generally, a conventional tray-based IC device handling system includes a tray source, a pick-and-place mechanism, and an alignment mechanism. The tray source is configured to move processing trays between processing stations. The pick-and-place mechanism is configured for removing individual IC devices from a processing tray and, further, for transferring the IC devices to a processing station. The pick-and-place mechanism has an extraction head adapted to lift, or “pick,” an IC device from its cell on a processing tray.
In order for an IC device to be extracted, or “picked,” from a processing tray, the extraction head of the pick-and-place mechanism must be aligned with the cell in which that IC device rests. Alignment between the extraction head and the cell is achieved by the alignment mechanism. The alignment mechanism includes a multi-dimensional motion system capable of accurately positioning a processing tray relative to the pick-and-place mechanism. The tray source, pick-and-place mechanism, and alignment mechanism, or any combination thereof, may form part of a single, integrated system.
Tray-based IC device handling systems tend to be slow and inefficient. Positioning systems, such as the tray source and the alignment mechanism, generally move at slow speeds relative to the pace at which other processing equipment can operate. Because conventional processing trays are configured to receive only a two-dimensional array of IC devices—each cell of the processing tray accepting only a single IC device—the tray-based IC device handling system must align a cell of the processing tray with the extraction head of the pick-and-place mechanism after the removal of every individual IC device from the processing tray. The necessity of aligning a different cell with the extraction head after the removal of each IC device results in inefficient handling and processing of IC devices. Also, because only a two-dimensional array of IC devices can be disposed on any conventional processing tray, a large number of processing trays are required.
Thus, a need exists in the semiconductor industry for a method and apparatus for processing large numbers of IC devices using a tray-based IC device handling system that is efficient, both in terms of processing time and in terms of reducing the number of required processing trays.